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CY7C1340F
4-Mb (128K x 32) Pipelined DCD Sync SRAM
Features
* Registered inputs and outputs for pipelined operation * Optimal for performance (Double-Cycle deselect) -- Depth expansion without wait state * 128K x 32-bit common I/O architecture * 3.3V -5% and +10% core power supply (VDD) * 3.3V / 2.5V I/O supply (VDDQ) * Fast clock-to-output times -- 2.6 ns (for 250-MHz device) -- 2.6 ns (for 225-MHz device) -- 2.8 ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) -- 4.0 ns (for 133-MHz device) -- 4.5 ns (for 100-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous Output Enable * JEDEC-standard 100-pin TQFP package and pinout * "ZZ" Sleep Mode option
Functional Description[1]
The CY7C1340F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1340F operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputsand outputs are JEDEC-standard JESD8-5-compatible..
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 325 40 225 MHz 2.6 290 40 200 MHz 2.8 265 40 166 MHz 3.5 240 40 133 MHz 4.0 225 40 100 MHz 4.5 205 40 Unit ns mA mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05219 Rev. *A
*
3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised January 19, 2004
CY7C1340F
Functional Block Diagram--128Kx32
ADDRESS REGISTER
2 A[1:0]
A0,A1,A
MODE ADV CLK
BURST LOGIC
Q1
COUNTER AND
CLR ADSC ADSP BWD DQD BYTE WRITE REGISTER DQc BYTE WRITE REGISTER DQB BYTE WRITE REGISTER DQA BYTE WRITE REGISTER ENABLE REGISTER
Q0
DQD BYTE WRITE DRIVER DQC BYTE WRITE DRIVER DQB BYTE WRITE DRIVER DQA BYTE WRITE DRIVER
MEMORY ARRAY SENSE AMPS
BWC
OUTPUT REGISTERS
OUTPUT BUFFERS
E
DQs
BWB
BWA BWE GW CE1 CE2 CE3 OE
INPUT REGISTERS
PIPELINED ENABLE
ZZ
SLEEP CONTROL
Document #: 38-05219 Rev. *A
Page 2 of 17
CY7C1340F
Pin Configurations
100-pin TQFP Top View
BYTE C
BYTE D
NC DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A A
CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
CY7C1340F (128K x 32)
NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC
BYTE B
BYTE A
MODE A A A A A1 A0
NC NC VSS VDD
NC NC
A
Document #: 38-05219 Rev. *A
A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1340F
Pin Descriptions
Pin A0, A1, A TQFP 37,36,32,33 34,35,44,45, 46,47,48,49, 50,81,82,99, 100 93,94,95,96 88 Type Description InputAddress Inputs used to select one of the 128K address locations. Sampled at Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] are fed to the two-bit counter. InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes Synchronous to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous signal must be asserted LOW to conduct a byte write. InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
BWA, BWB, BWC, BWD GW
BWE CLK CE1 CE2 CE3 OE
87 89 98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronous DQ pins. When LOW, the DQ pins behave as outputs. When deasserted HIGH, DQ pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When Synchronous asserted, it automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a Asynchronous non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs are placed in a three-state condition.
97 92 86
ADV ADSP
83 84
ADSC
85
ZZ
64
DQs
52,53,56,57, 58,59,62,63 68,69,72,73, 74,75,78,79 2,3,6,7,8,9, 12,13 18,19,22,23, 24,25,28,29 15,41,65, 91 17,40,67, 90 4,11,20,27, 54,61,70,77
VDD VSS VDDQ
Power Supply Power supply inputs to the core of the device. Ground I/O Power Supply Ground for the core of the device. Power supply for the I/O circuitry.
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CY7C1340F
Pin Descriptions (continued)
Pin VSSQ MODE TQFP 5,10,21,26, 55,60,71,76 31 Type I/O Ground InputStatic Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not internally connected to the die. Description
NC
14,16,38,39, 42,43,66,1, 30,51,80
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1340F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1340F is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately after the next clock rise.
Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BW[A:D] signals. The CY7C1340F provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1340F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1340F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will three-state the output drivers. As a safety precaution, DQX are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Page 5 of 17
Document #: 38-05219 Rev. *A
CY7C1340F
Burst Sequences
The CY7C1340F provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZ tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
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CY7C1340F
Truth Table [2, 3, 4, 5, 6]
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down ZZ Mode, Power-Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used CE1 CE2 CE3 None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L X L L L L L X X H H X H X X H H X H X L X L X X H H H H H X X X X X X X X X X X X X X H X H X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP ADSC X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK DQ
L-H Three-State L-H Three-State L-H Three-State L-H Three-State L-H Three-State X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H Three-State Q D Q Q Q D D Q Q D D
L-H Three-State
L-H Three-State L-H Three-State L-H Three-State
L-H Three-State L-H Three-State
Partial Truth Table for Read/Write[2, 7]
Function Read Read Write byte A - DQA Write byte B - DQB Write byte C - DQC Write byte D - DQD Write all bytes Write all bytes GW H H H H H H H L BWE H L L L L L L X BWA X H L H H H L X BWB X H H L H H L X BWC X H H H L H L X BWD X H H H H L L X
Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). 7. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active.
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CY7C1340F
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................... -65C to +150 Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in Three-State ..................................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V Current into Outputs (LOW) .........................................20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883,Method 3015) Latch -up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature (TA) 0C to +70C -40C to +85C VDD VDDQ
3.3V -5%/+10% 2.5V -5% to VDD
Electrical Characteristics Over the Operating Range[8, 9]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[8] Voltage[8] VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -2.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Input Load Current except ZZ GND VI VDDQ and MODE Input Current of MODE Input Current of ZZ IOZ IDD Output Leakage Current VDD Operating Supply Current Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 4.4-ns cycle, 225 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz ISB1 Automatic CE Power-down Current--TTL Inputs VDD = Max., Device Deselected, 4-ns cycle, 250 MHz VIN VIH or VIN VIL, f = fMAX = 4.4-ns cycle, 225 MHz 1/tCYC 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz
Shaded areas contain advance information. Notes: 8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Test Conditions
Min. 3.135 2.375 2.4 2.0
Max. 3.6 VDD
Unit V V V V
0.4 0.4 2.0 1.7 -0.3 -0.3 -5 -30 5 -5 30 -5 5 325 290 265 240 225 205 120 115 110 100 90 80 VDD + 0.3V VDD + 0.3V 0.8 0.7 5
V V V V V V A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA
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CY7C1340F
Electrical Characteristics Over the Operating Range[8, 9]
Parameter ISB2 ISB3 Description Automatic CE Power-down Current--CMOS Inputs Automatic CE Power-down Current--CMOS Inputs Test Conditions VDD = Max., Device Deselected, All speeds VIN 0.3V or VIN > VDDQ - 0.3V, f=0 VDD = Max., Device Deselected, 4-ns cycle, 250 MHz or VIN 0.3V or VIN > VDDQ - 4.4-ns cycle, 225 MHz 0.3V, f = fMAX = 1/tCYC 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz ISB4 Automatic CE Power-down Current--TTL Inputs VDD = Max., Device Deselected, All speeds VIN VIH or VIN VIL, f = 0 Min. Max. 40 Unit mA
105 100 95 85 75 65 45
mA mA mA mA mA mA mA
Thermal Characteristics[10]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package 41.83 9.99 Unit C/W C/W
Capacitance[10]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ = 3.3V Max. 5 5 5 Unit pF pF pF
Note: 10. Tested initially and after any design or process change that may affect these parameters.
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CY7C1340F
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 R = 317 VDD 5 pF GND R = 351 10% ALL INPUT PULSES 90% 90% 10% 1ns
VL = 1.5V
1ns
(a) 2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V
INCLUDING JIG AND SCOPE
(b)
(c)
R = 1667 VDD 5 pF GND R =1538 10%
ALL INPUT PULSES 90% 90% 10% 1ns
OUTPUT RL = 50 VL = 1.25V
1ns
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
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CY7C1340F
Switching Characteristics Over the Operating Range
250 MHz Parameter tPOWER Clock tCYC tCH tCL tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Clock Cycle Time Clock HIGH Clock LOW Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[12, 13, 14] Clock to High-Z[12, 13, 14] 0 2.6 OE LOW to Output Valid OE LOW to Output Low-Z[12, 13, 14] 1.0 0 2.6 2.6 0 2.6 4.0 1.7 1.7 2.6 1.0 0 2.6 2.6 0 2.8 4.4 2.0 2.0 2.6 1.0 0 2.8 2.8 0 3.5 5.0 2.0 2.0 2.8 2.0 0 3.5 3.5 0 4.0 6.0 2.5 2.5 3.5 2.0 0 4.0 4.5 0 4.5 7.5 3.0 3.0 4.0 2.0 0 4.5 4.5 10 3.5 3.5 4.5 ns ns ns ns ns ns ns ns ns ns Description VDD(Typical) to the first Access[11] 1.0
[15, 16]
225 MHz 1.0
200 MHz 1.0
166 MHz 1.0
133 MHz 1.0
100 MHz 1.0 ms
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Output Times
OE HIGH to Output [12, 13, 14] High-Z Set-up Times tAS tADS tADVS tWES tDS tCES Address Set-up Before CLK Rise ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BW[A:D] Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up Before CLK Rise Address Hold After CLK Rise ADSP , ADSC Hold After CLK Rise ADV Hold After CLK Rise GW,BWE, BW[A:D] Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.8 0.8 0.8 0.8 0.8 0.8
1.2 1.2 1.2 1.2 1.2 1.2
1.2 1.2 1.2 1.2 1.2 1.2
1.5 1.5 1.5 1.5 1.5 1.5
1.5 1.5 1.5 1.5 1.5 1.5
1.5 1.5 1.5 1.5 1.5 1.5
ns ns ns ns ns ns
Hold Times tAH tADH tADVH tWEH tDH tCEH 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns
Shaded areas contain advance information. Notes: 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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CY7C1340F
Switching Waveforms
Read Timing[17]
tCYC
CLK
tCH tADS tADH tCL
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
tWES tWEH
A2
A3 Burst continued with new base address
GW, BWE,BW
[A:D] tCES tCEH
Deselect cycle
CE
tADVS tADVH
ADV ADV suspends burst OE
tOEV t CLZ t OEHZ t OELZ tCO tDOH t CHZ
Data Out (Q)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Single READ
BURST READ
Burst wraps around to its initial state
DON'T CARE
UNDEFINED
Note: 17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05219 Rev. *A
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CY7C1340F
Switching Waveforms (continued)
Write Timing[17, 18]
t CYC
CLK
tCH tADS tADH tCL
ADSP
tADS tADH
ADSC extends burst
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BW[A:D]
tWES tWEH
GW
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t DS t DH
Data in (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE DON'T CARE UNDEFINED
Extended BURST WRITE
Note: 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: 38-05219 Rev. *A
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CY7C1340F
Switching Waveforms (continued)
Read/Write Timing[17, 19, 20]
tCYC
CLK
tCH tADS tADH tCL
ADSP
ADSC
tAS tAH
ADDRESS BWE, BW[A:D]
A1
A2
A3
tWES tWEH
A4
A5
A6
tCES tCEH
CE
ADV
OE
tCO tDS tDH tOELZ
Data In (D) Data Out (Q)
High-Z
tCLZ
tOEHZ
D(A3)
D(A5)
D(A6)
High-Z
Q(A1) Back-to-Back READs
Q(A2) Single WRITE DON'T CARE
Q(A4)
Q(A4+1) BURST READ UNDEFINED
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
Notes: 19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20. GW is HIGH.
Document #: 38-05219 Rev. *A
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CY7C1340F
Switching Waveforms (continued)
ZZ Mode Timing [21, 22]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 21. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode.
Ordering Information
Speed (MHz) 250 225 200 166 133 100 Ordering Code CY7C1340F-250AC CY7C1340F-250AI CY7C1340F-225AC CY7C1340F-225AI CY7C1340F-200AC CY7C1340F-200AI CY7C1340F-166AC CY7C1340F-166AI CY7C1340F-133AC CY7C1340F-133AI CY7C1340F-100AC CY7C1340F-100AI Package Name A101 A101 A101 A101 A101 A101 A101 A101 A101 A101 A101 A101 Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05219 Rev. *A
Page 15 of 17
CY7C1340F
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05219 Rev. *A
Page 16 of 17
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1340F
Document History Page
Document Title: CY7C1340F 4-Mb (128K x 32) Pipelined DCD Sync SRAM Document Number: 38-05219 REV. ** *A ECN NO. 119827 200143 Issue Date 12/16/02 See ECN Orig. of Change HGK SWI New Data Sheet Final Data Sheet Description of Change
Document #: 38-05219 Rev. *A
Page 17 of 17

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